Electronic packaging refers to the physical implementations of electrical circuits of integrated circuit (IC) chips, modules, chip or module carriers, cards, boards or backplanes. Such components and devices are often referred to as electronic packaging structures. The terms "electronic packaging structure" "electronic package" and "package" are hereinafter used interchangeably to refer to any or all of the aforementioned devices and structures. For purposes of this discussion, such structures include multilayered packaging, in which a plurality of substantially parallel conductive planes (designated as ground and/or power or voltage planes) are separated from one another by non-conductive dielectric material. In addition to power and ground planes, signal paths or traces for carrying dynamic information are routed on additional substantially parallel layers interposed between voltage and/or ground planes. These layers of signal traces are also isolated from power/ground planes and from each other by dielectric layers. Via pins are utilized to connect planes and/or traces to other planes and/or traces or to form connections external to the package structure. The power and ground planes, together with the vias connected thereto, provide the power and ground supply system for IC chips, whereas signal traces, together with the vias connected thereto, provide electrical interconnections between chips and circuits both internal and external to the package. Because signal traces are embedded in dielectric media sandwiched between conductive planes, interactions take place between currents carried on signal traces and voltage fluctuations on these conductive planes.
More specifically, currents flowing in signal traces and/or vias may induce voltage fluctuations between adjacent ground and/or power planes. Likewise, voltage fluctuations between adjacent power and/or ground planes may induce spurious currents in signal traces and/or vias. These interactions may be so severe that the integrity of the signal being carried on a particular trace/via may be adversely, perhaps even catastrophically affected.
It has long been the practice of digital electronic system designers to employ simulation techniques to predict the ultimate behavior of those systems before the actual hardware implementation thereof. As large-scale integration (LSI) and very large-scale integration (VLSI) techniques have allowed greater numbers of circuits to be packaged in smaller spaces, it has become increasingly difficult to construct physical prototypes of proposed digital systems prior to the actual construction of the chip. Therefore, although the simulation of proposed systems was once merely advisable, it is now necessary.
Because of ever-increasing IC transition speed, power/ground noise (known as simultaneous switching noise SSN! or delta-I noise) has posed a significant challenge to reliable, high-speed IC operation. Numerous problems arising therefrom (such as larger delays, the loss of signal integrity and false switching of devices) can lead to the malfunctioning of overall systems.
SSN or delta-I noise is generated when a logic gate changes state, thereby altering the current flow in a system. The resulting change in current (delta-I) induces transient voltage variations in nearby metallic planes and/or conductors. Of particular interest are voltages induced in the voltage supply and/or ground planes that are usually found in multilayered packages. The effects of noise on actual hardware must be accounted for in any system simulation in order for the simulation to predict true hardware system performance.
In the aforementioned co-pending application, Ser. No. 08/325,006, a novel technique for modeling the influence of voltage fluctuations between planes in an electronic packaging structure is taught. That technique, however, does not account for interactions between signal traces and/or signal vias and power and ground planes. Heretofore, accounting for these types of interactions has been beyond the capabilities of any practical simulation tools.
It is an object of the present invention to provide a method for simulating an electronic packaging structure wherein effects of interactions of signal traces and/or vias with planes and vice versa are fully considered.
It is a further object of the invention to present a computationally efficient method for simulating such interactions.
It is yet a further object of the invention to provide a method compatible with existing numerical simulation systems.